According to the notification, the scheme has six pillars and 10 categories covering the semiconductor value chain. It aims to build a self-reliant and globally competitive semiconductor design and manufacturing ecosystem, strengthen supply-chain resilience and establish technological capabilities in critical sectors.
The notification follows the government’s approval in July of a Rs 1,27,500 crore outlay for Semicon 2.0. The first phase, Semicon India 1.0, had an outlay of Rs 76,000 crore. The 31 August notification sets out the framework through which companies and institutions can seek support under the second phase.
At a press conference, Union Minister for Electronics and Information Technology Ashwini Vaishnaw said the reduction in fiscal support for silicon semiconductor wafer fabs from 50 per cent under the first phase to 40 per cent under Semicon 2.0 should not discourage investors.
“When we started Semiconductor 1.0 in 2022, at that time the global semiconductor industry majors had serious doubts about whether this could really happen in a country. That doubt is no longer there. That doubt is now replaced by confidence,” Vaishnaw said.
The minister pointed out that the confidence was also reflected in the speed at which approved projects have progressed from groundbreaking to commercial production. “In one case, 13 months from the date of groundbreaking, commercial production started,” Vaishnaw said.
He also pointed out to cases where approvals were given within 200 days, 150 days and, in one case, 90 days.
Vaishnaw said companies consider the long-term prospects of establishing semiconductor operations in India rather than looking only at the incentive structure.
“The companies look at the long-term perspective of growth in India when they make these decisions. The incentive structure is an incidental part of it. It is not the core of the entire programme,” he explained.
Support for equipment and materials
The notification provides support for semiconductor equipment research and development (R&D), manufacturing facilities for semiconductor-grade raw materials, equipment and component manufacturing and semiconductor test and characterisation facilities.
For R&D facilities for semiconductor equipment and facilities manufacturing or assembling equipment, sub-assemblies and components used in semiconductor fabrication and packaging, the government will provide 30 per cent of eligible capital expenditure on a pari-passu basis.
For equipment and component manufacturing, the scheme also provides a production-linked incentive (PLI) of 10 per cent, 8 per cent, 6 per cent, 4 per cent and 2 per cent of the bill-of-materials value sourced from domestic manufacturers. The incentive will apply for five years from FY2028-29 and will be subject to an overall ceiling of 50 per cent of eligible capital expenditure.
The notification lists semiconductor-grade raw materials such as wafers, photomasks, photoresists, substrates, chemicals and gases among the targeted areas.
Vaishnaw said the government expects equipment manufacturers and their suppliers to establish operations in India.
“Our focus in this version of Semicon is to make sure that the ecosystem takes very deep roots and over the next few months you will see almost every major equipment manufacturer will be setting up their base in India,” he said. This could also create opportunities for smaller manufacturers supplying components and precision parts to semiconductor equipment manufacturers, he added.
40% support for silicon wafer fabs
For silicon semiconductor wafer fabs, Semicon 2.0 provides fiscal support of 40 per cent of eligible capital expenditure on a pari-passu basis.
The category covers 300-mm wafer fabs with an installed capacity of at least 40,000 wafer starts per month. Applicants must possess production-grade licensed technology for the proposed process and have a minimum capital investment of Rs 20,000 crore and a minimum revenue of Rs 7500 crore in any one of the three financial years preceding the year of application.
For compound semiconductor, photonics, sensors, including MEMS and discrete semiconductor fabs, the notification provides fiscal support of 35 per cent of eligible capital expenditure. The minimum capital investment threshold is Rs 500 crore.
Advanced packaging
The scheme also provides support for semiconductor Assembly, Testing, Marking and Packaging (ATMP) and Outsourced Semiconductor Assembly and Test (OSAT) facilities.
Advanced packaging technologies, including 2.5D and 3D packaging, wafer-level chip-scale packaging and heterogeneous integration, will be eligible for 35 per cent fiscal support on eligible capital expenditure. Legacy packaging projects will receive 25 per cent support. The minimum capital investment threshold for both categories is Rs 1000 crore.
One lakh more engineers
Talent development is the sixth pillar of the scheme. The notification provides fiscal support of up to 75 per cent of project cost, including capex and opex and state incentives. It covers training across undergraduate, postgraduate and doctoral levels as well as shop-floor technicians and operators.
Vaishnaw said the government had earlier targeted developing 85,000 semiconductor engineers and achieved that target in four years instead of the planned 10 years.
“Now we plan to increase the target to 1 lakh more engineers,” he said.
Industry estimates put the semiconductor talent gap at about one million by 2032, Vaishnaw added.
On manufacturing talent, training would cover workers required for fabs, packaging, equipment and materials, he said. He estimated that the developing ecosystem could create 50,000-60,000 direct jobs every year in manufacturing, in addition to the jobs being created in semiconductor design.
R&D and chip design
The R&D category provides fiscal support of up to 75 per cent of project cost, including capital expenditure (capex) and operating expenses (opex) and state incentives. The notification identifies advanced CMOS fabrication, silicon photonics, display fabrication and chiplet-based technologies for advanced packaging among the areas that can be supported.
For commercial semiconductor design, the scheme provides access to design infrastructure, including national EDA tools, multi-project wafer fabrication services and post-silicon validation services. Eligible startups and MSMEs can receive milestone-linked seed funding of up to Rs 15 crore, limited to 50 per cent of the project cost or Rs 15 crore, whichever is lower.
The scheme also provides a deployment-linked incentive (DLI) for semiconductor IPs, chips and SoCs. Eligible products can receive reimbursement of 9 per cent of net sales for five years, subject to a maximum incentive of Rs 30 crore per application and an aggregate ceiling of Rs 120 crore per company.
Vaishnaw said larger companies would also be able to participate in the design incentive programme. He cited companies such as L&T and Tata as examples of companies that could establish design houses and develop semiconductor products under the scheme.
India targets global value chains
The minister said India’s objective is to become embedded at multiple points in the global semiconductor value chain.
“People should feel dependent on India. People should become dependent on our country, on our industry, on our production, on our design,” he said.
The Minister added that India could account for close to 10 per cent of the global semiconductor industry market in the coming years.
The scheme will initially be open for applications for three years, while individual projects can run for up to six years. The India Semiconductor Mission (ISM) has been designated as the nodal agency and will invite applications, conduct technical and financial appraisal and recommend applicants for selection.
Vaishnaw said the government would prioritise the quality of projects rather than the number of approvals.
“Quality is more important than quantity,” he said. The government was looking at a 20-30 year development journey for the semiconductor industry, pointed out.